ppc64-diag
dchrp.h
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1 
21 #ifndef _H_DCHRP
22 #define _H_DCHRP
23 
24 /*
25  * Error log identifiers that are built as follows:
26  *
27  * bit number:
28  * 3322222222221111111111
29  * 10987654321098765432109876543210
30  * --------------------------------
31  * 0000
32  * ----
33  * | --------
34  * | |
35  * | | --------
36  * | | | --------
37  * | | | |
38  * | | | if cpu, mem, post or io format
39  * | | | extended log byte 12
40  * | | | if epow format
41  * | | | extended log byte 15
42  * | | | if sp format
43  * | | | extended log byte 16
44  * | | |
45  * | | if mem, post or io format
46  * | | extended log byte 13
47  * | | if sp format
48  * | | extended log byte 17
49  * | | if epow format
50  * | | extended log byte 16
51  * | |
52  * | if sp format
53  * | extended log byte 18
54  * | if epow format
55  * | extended log byte 17
56  * |
57  * extended log byte 2, bits 4:7
58  *
59  *
60  * and each ID is labeled xxxByybz where xxx= format,yy=byte #,z=bit #
61  * and Byybz is repeated as often as necessary
62  *
63  */
64 #define CPUB12b0 0x01000080
65 #define CPUB12b1 0x01000040
66 #define CPUB12b2 0x01000020
67 #define CPUB12b3 0x01000010
68 #define CPUB12b4 0x01000008
69 #define CPUB12b5 0x01000004
70 #define CPUB12b6 0x01000002
71 #define CPUB12b7 0x01000001
72 #define CPUALLZERO 0x01000000
73 #define MEMB12b0 0x02000080
74 #define MEMB12b1 0x02000040
75 #define MEMB12b2 0x02000020
76 #define MEMB12b3 0x02000010
77 #define MEMB12b4 0x02000008
78 #define MEMB12b4B13b3 0x02001008
79 #define MEMB12b5 0x02000004
80 #define MEMB12b6 0x02000002
81 #define MEMB12b7 0x02000001
82 #define MEMB13b0 0x02008000
83 #define MEMB13b1 0x02004000
84 #define MEMB13b2 0x02002000
85 #define MEMB13b3 0x02001000
86 #define MEMB13b4 0x02000800
87 #define MEMALLZERO 0x02000000
88 #define IOB12b0 0x03000080
89 #define IOB12b1 0x03000040
90 #define IOB12b2 0x03000020
91 #define IOB12b3 0x03000010
92 #define IOB12b3B13b2 0x03002010
93 #define IOB12b4 0x03000008
94 #define IOB12b5 0x03000004
95 #define IOB12b6 0x03000002
96 #define IOB12b7 0x03000001
97 #define IOB12b5B13b0 0x03008004
98 #define IOB12b6B13b0 0x03008002
99 #define IOB12b7B13b0 0x03008001
100 #define IOB12b5B13b1 0x03004004
101 #define IOB12b6B13b1 0x03004002
102 #define IOB12b7B13b1 0x03004001
103 #define IOB12b5B13b2 0x03002004
104 #define IOB12b6B13b2 0x03002002
105 #define IOB12b7B13b2 0x03002001
106 #define IOB12b6B13b3 0x03001002
107 #define IOB13b4 0x03000800
108 #define IOB13b5 0x03000400
109 #define IOB13b6 0x03000200
110 #define IOB13b7 0x03000100
111 #define IOALLZERO 0x03000000
112 #define POSTALLZERO 0x04000000
113 #define POSTB12b0 0x04000080
114 #define POSTB12b1 0x04000040
115 #define POSTB12b2 0x04000020
116 #define POSTB12b3 0x04000010
117 #define POSTB12b4 0x04000008
118 #define POSTB12b5 0x04000004
119 #define POSTB12b6 0x04000002
120 #define POSTB12b7 0x04000001
121 #define POSTB13b0 0x04008000
122 #define POSTB13b1 0x04004000
123 #define POSTB13b2 0x04002000
124 #define POSTB13b3 0x04001000
125 #define POSTB13b4 0x04000800
126 #define POSTB13b5 0x04000400
127 #define POSTB13b7 0x04000100
128 #define EPOWB1501 0x05000001
129 #define EPOWB1501B16b2b4 0x05002801
130 #define EPOWB1502 0x05000002
131 #define EPOWB1502B16b4 0x05000802
132 #define EPOWB1503 0x05000003
133 #define EPOWB1503B16b23 0x05003003
134 #define EPOWB1503B16b3 0x05001003
135 #define EPOWB1504 0x05000004
136 #define EPOWB1505 0x05000005
137 #define EPOWB1505B16b1B17b1 0x05404005
138 #define EPOWB1505B16b1B17b2 0x05204005
139 #define EPOWB1505B16b1B17b3 0x05104005
140 #define EPOWB1502B16b4B17b2 0x05200802
141 #define EPOWB1502B16b1b4B17b2 0x05204802
142 #define EPOWB1507 0x05000007
143 #define SPB16b0 0x0D000080
144 #define SPB16b1 0x0D000040
145 #define SPB16b2 0x0D000020
146 #define SPB16b3 0x0D000010
147 #define SPB16b4 0x0D000008
148 #define SPB16b5 0x0D000004
149 #define SPB16b6 0x0D000002
150 #define SPB16b7 0x0D000001
151 #define SPB17b0 0x0D008000
152 #define SPB17b1 0x0D004000
153 #define SPB17b2 0x0D002000
154 #define SPB17b3 0x0D001000
155 #define SPB17b4 0x0D000800
156 #define SPB17b5 0x0D000400
157 #define SPB17b6 0x0D000200
158 #define SPB17b7 0x0D000100
159 #define SPB18b0 0x0D800000
160 #define SPB18b1 0x0D400000
161 #define SPB18b2 0x0D200000
162 #define SPB18b3 0x0D100000
163 #define SPB18b4 0x0D080000
164 #define SPB18b5 0x0D040000
165 #define SPB18b6 0x0D020000
166 #define SPB18b7 0x0D010000
167 #define EPOWLOGB16b0 0x05008000
168 #define LOGB16b4 0x00000800
169 
170 #define EPOWLOG 0x05000000
171 #define SPLOG 0x0D000000
172 
173 /*
174  * Bits analyzed in Version 2 EPOW logs.
175  */
176 #define EPOWB16b0 0x00008000
177 #define EPOWB16b1 0x00004000
178 #define EPOWB16b2 0x00002000
179 #define EPOWB16b3 0x00001000
180 #define EPOWB16b2b3 0x00003000
181 #define EPOWB16b4 0x00000800
182 #define EPOWB17b0 0x00800000
183 #define EPOWB17b1 0x00400000
184 #define EPOWB17b2 0x00200000
185 #define EPOWB17b3 0x00100000
186 #define EPOWB17b4 0x00080000
187 
188 /*
189  * Extened EPOW codes, found after the location codes. The sensor nibble
190  * is ignored.
191  */
192 #define XEPOW1n11 0x1011
193 #define XEPOW1n64 0x1064
194 #define XEPOW2n32 0x2032
195 #define XEPOW2n52 0x2052
196 #define XEPOW3n21 0x3021
197 #define XEPOW3n73 0x3073
198 
199 #define IGNORE_SENSOR_MASK 0xF0FF
200 
201 /*
202  * PCI EPOW Register values for bits 13:15
203  */
204 #define PCIEPOW111 0x00070000
205 #define PCIEPOW100 0x00040000
206 #define PCIEPOW011 0x00030000
207 #define PCIEPOW010 0x00020000
208 #define PCIEPOW001 0x00010000
209 
210 #define PCIEPOWMASK 0x00070000
211 
212 
213 #define CRITHI 13
214 #define CRITLO 9
215 #define WARNHI 12
216 #define WARNLO 10
217 #define NORMAL 11
218 #define GS_SUCCESS 0
219 
220 #define THERM 3
221 #define POWER 9004
222 #define VOLT 9002
223 #define FAN 9001
224 
225 /*
226  * Offsets into the chrp error log
227  */
228 #define I_EXTENDED 8 /* index to extended error log */
229 #define I_BYTE0 0 + I_EXTENDED /* contains predicative error bit */
230 #define I_BYTE1 1 + I_EXTENDED /* has platform specific error bit */
231 #define I_FORMAT 2 + I_EXTENDED /* to log format indicator */
232 #define I_BYTE3 3 + I_EXTENDED /* has modifier bits */
233 #define I_BYTE12 12+ I_EXTENDED /* to bytes describing error, where */
234 #define I_BYTE13 13+ I_EXTENDED /* most formats use bytes 12 & 13 */
235 #define I_BYTE15 15+ I_EXTENDED /* for epow errors */
236 #define I_BYTE16 16+ I_EXTENDED /* for sp errors */
237 #define I_BYTE17 17+ I_EXTENDED /* for sp errors */
238 #define I_BYTE18 18+ I_EXTENDED /* for sp errors */
239 #define I_BYTE19 19+ I_EXTENDED /* for sp errors */
240 #define I_BYTE24 24+ I_EXTENDED /* for repair pending bit */
241 #define I_BYTE28 28+ I_EXTENDED /* for sp errors */
242 #define I_CPU 13+ I_EXTENDED /* to for physical cpu number */
243 #define I_POSTCODE 26+ I_EXTENDED /* to post error code */
244 #define I_FWREV 30+ I_EXTENDED /* to firmware revision level */
245 #define I_IBM 40+ I_EXTENDED /* to IBM id for location codes */
246 #define I_TOKEN 20+I_EXTENDED
247 #define I_INDEX 24+I_EXTENDED
248 #define I_STATUS 32+I_EXTENDED
249 
250 #define IGNORE_SENSOR_MASK 0xF0FF /* for extended epow, a 2 byte value */
251 #define SENSOR_MASK 0x0F00
252 #define EXT_EPOW_REG_ID 0x3031 /* ascii for 01 */
253 #define SRC_REG_ID_02 0x3032 /* Ascii for 02 */
254 #define PCI_EPOW_REG_ID 0x3033
255 #define SRC_REG_ID_04 0x3034 /* Ascii for 04 */
256 
257 /* Structure to describe i/o device from i/o detected chrp log */
258 struct device_ela {
259  int status; /* 0=no data;1=bus only;2=device ok */
260  char bus;
261  char devfunc;
262  short deviceid;
263  short vendorid;
265  char slot;
266  char name[NAMESIZE];
268  char loc[LOCSIZE];
269  short led;
270 };
271 #define DEVICE_NONE 0
272 #define DEVICE_BUS 1
273 #define DEVICE_OK 2
274 
275 #define FIRST_LOC 1 /* mode for first location code */
276 #define NEXT_LOC 2 /* mode for next location code */
277 #define FIRST_REG 1 /* mode for first register data */
278 #define NEXT_REG 2 /* mode for next register data */
279 
280 #define LOC_HIDE_CHAR '>' /* special meaning in location code buffer */
281 
282 /* Return codes from get_cpu_frus */
283 #define RC_INVALID 0
284 #define RC_PLANAR 1
285 #define RC_PLANAR_CPU 2
286 #define RC_PLANAR_2CPU 3
287 
288 #define MAXREFCODES 5
289 #define REFCODE_REASON_CUST 0x880
290 
291 /*
292  * The following name is a flag for the diag controller to format
293  * the error description into a "special" SRN, i.e. containing refcodes
294  */
295 #define REFCODE_FNAME "REF-CODE"
296 
297 #define MAX_MENUGOAL_SIZE 2000
298 
299 #endif
char revisionid
Definition: dchrp.h:264
char busname[NAMESIZE]
Definition: dchrp.h:267
char bus
Definition: dchrp.h:260
int status
Definition: dchrp.h:259
short deviceid
Definition: dchrp.h:262
char name[NAMESIZE]
Definition: dchrp.h:266
Definition: dchrp.h:258
#define NAMESIZE
Definition: fru_prev6.h:24
char loc[LOCSIZE]
Definition: dchrp.h:268
char devfunc
Definition: dchrp.h:261
short vendorid
Definition: dchrp.h:263
#define LOCSIZE
Definition: fru_prev6.h:25
short led
Definition: dchrp.h:269
char slot
Definition: dchrp.h:265